This invention relates to a processor, and in particular to the compression of instructions used by the processor.
In order to operate a processor, it is necessary to store a set of instructions for the operation of the processor. That is, there is typically associated with a processor a memory, which can be used to store the instructions that the processor will use. In some environments, the storage of these instructions can occupy a significant part of the available memory resources. It is known that it can be advantageous to apply some form of compression to the instructions where possible. Programs are stored into the memory in compressed format, then decompressed in the instruction decoding phase, and then executed in the processor.
It has been noted, in the document “Code Compression on Transport Triggered Architectures”, J. Heikkinen et al., Proc. Int. Workshop on System-on-Chip for Real-Time Applications, Banff, Canada, Jul. 6-7 2002, pp. 186-195, that, in some applications, information is available about the probabilities of occurrence of each possible instruction. This information can be used to increase the efficiency of the coding of the instructions by using a form of entropy coding. That is, instructions that are expected to occur more frequently are encoded to a shorter code, while instructions that are expected to occur less frequently are encoded to a longer code, with the result that the average code length is reduced.